Allwinner A20 - Page 751

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 751 / 812
Offset: 0x14
Register Name: TSC_PPARR
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
1
DVALID signal polarity
0: High level active
1: Low level active
0
PSYNC signal polarity
0: High level active
1: Low level active
7:0
R/W
0x00
TSInPort0Par
TS Input Port0 Parameters
Bit
Definition
7:5
Reserved
4
SSI data order
0: MSB first for one byte data
1: LSB first for one byte data
3
CLOCK signal polarity
0 : Rise edge capturing
1: Fall edge capturing
2
ERROR signal polarity
0: High level active
1: Low level active
1
DVALID signal polarity
0: High level active
1: Low level active
0
PSYNC signal polarity
0: High level active
1: Low level active
6.13.4.5. TSC TSF INPUT MULTIPLEX CONTROL REGISTER
Offset: 0x20
Register Name: TSC_TSFMUXR
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
31:8
/
/
/
7:4
R/W
0x0
TSF1InputMuxCtrl
TSF1 Input Multiplex Control
0x0 –Data from TSG
0x1 –Data from TS IN Port0
0x2 –Data from TS IN Port1
Others – Reserved
3:0
R/W
0x0
TSF0InputMuxCtrl