Allwinner A20 - Page 760

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 760 / 812
6.13.4.17. TSF DMA INTERRUPT ENABLE REGISTER
Offset: TSF+0x10
Register Name: TSF_DIER
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
31:0
R/W
0x0
DMAIE
DMA Interrupt Enable
DMA interrupt enable bits for channel 0~31.
6.13.4.18. TSF OVERLAP INTERRUPT ENABLE REGISTER
Offset: TSF+0x14
Register Name: TSF_OIER
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
31:0
R/W
0x0
OLPIE
Overlap Interrupt Enable
Overlap interrupt enable bits for channel 0~31.
6.13.4.19. TSF DMA INTERRUPT STATUS REGISTER
Offset: TSF+0x18
Register Name: TSF_DISR
Default Value: 0x3FFF_0000
Bit
Read/Write
Default
Description
31:0
R/W
0x0
DMAIS
DMA Interrupt Status
DMA interrupt Status bits for channel 0~31.
Set by hardware, and can be cleared by software writing ‘1’.
When both these bits and the corresponding DMA Interrupt
Enable bits set, the TSF interrupt will generate.