Allwinner A20 - Page 772

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 772 / 812
Offset: 0x0000
Register Name: SCR_CSR
Default Value: 0x00000000
Bit
Read/Write
Default
Description
0: Low Active
1: High Active
23:22
R/W
0
Protocol Selection (PTLSEL)
0x0 – T=0.
0x1 – T=1, no character repeating and no guard time is used
when T=1 protocol is selected.
0x2 – Reserved
0x3 – Reserved
21
R/W
0
ATRSTFLUSH
ATR Start Flush FIFO
When enabled, both FIFOs are flushed before the ATR is
started.
20
R/W
0
TSRXE
TS Receive Enable
When set to ‘1’, the TS character (the first ATR character) will
be store in RXFIFO during card session.
19
R/W
0
CLKSTPPOL
Clock Stop Polarity
The value of the scclk output during the clock stop state.
18
R/W
0
PECRXE
Parity Error Character Receive Enable
Enables storage of the characters received with wrong parity
in RX FIFO.
17
R/W
0
MSBF
MSB First
When high, inverse bit ordering convention (msb to lsb) is
used.
16
R/W
0
DATAPOL
Data Plorarity
When high, inverse level convention is used (A=’1’, Z=’0’).
15:12
/
/
/
11
R/W
0
DEACTDeactivation. Setting of this bit initializes the
deactivation sequence. When the deactivation is finished, the
DEACT bit is automatically cleared.
10
R/W
0
ACT
Activation. Setting of this bit initializes the activation sequence.