Allwinner A20 - Page 775

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 775 / 812
Offset: 0x0004
Register Name: SCR_INTEN
Default Value: 0x00000000
Bit
Read/Write
Default
Description
TX FIFO Empty Interrupt Enable.
0
R/W
0
TXFIFODONE
TX FIFO Done Interrupt Enable.
6.14.5.3. SMART CARD READER INTERRUPT STATUS REGISTER
This 16-bit register provides information about the state of each interrupt bit. You can clear the
register bits individually by writing ‘1’ to a bit you intend to clear.
Offset: 0x0008
Register Name: SCR_INTST
Default Value: 0x00000000
Bit
Read/Write
Default
Description
31:24
/
/
/
23
R/W
0
SCDEA
Smart Card Deactivation Interrupt. When enabled, this
interrupt is asserted after the Smart Card deactivation
sequence is complete.
22
R/W
0
SCACT
Smart Card Activation Interrupt. When enabled, this interrupt is
asserted after the Smart Card activation sequence is
complete.
21
R/W
0
SCINS
Smart Card Inserted Interrupt. When enabled, this interrupt is
asserted after the smart card insertion.
20
R/W
0
SCREM
Smart Card Removed Interrupt. When enabled, this interrupt is
asserted after the smart card removal.
19
R/W
0
ATRDONE
ATR Done Interrupt. When enabled, this interrupt is asserted
after the ATR sequence is successfully completed.
18
R/W
0
ATRFAIL
ATR Fail Interrupt. When enabled, this interrupt is asserted if
the ATR sequence fails.
17
R/W
0
C2CFULL
Two Consecutive Characters Limit Interrupt. When enabled,
this interrupt is asserted if the time between two consecutive