Allwinner A20 - Page 78

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 78 / 812
Offset: 0x114
Register Name: MP_CLK_REG
Bit
Read/
Write
Default/Hex
Description
31
R/W
0x0
SCLK_GATING.
Gating Special Clock
0: Clock is OFF
1: Clock is ON
This special clock = Clock Source/Divider M.
30
R/W
0x0
MP_RST.
DE-MP Reset.
0: reset valid, 1: reset invalid.
29:26
/
/
/
25:24
R/W
0x0
CLK_SRC_SEL.
Clock Source Select
00: PLL3
01: PLL7
10: PLL5
11: /.
23:4
/
/
/
3:0
R/W
0x0
CLK_DIV_RATIO_M.
Clock divide ratio (m)
The pre-divided clock is divided by (m+1). The divider is
from 1 to 16.
1.5.4.49. LCD 0 CH0 CLOCK(DEFAULT: 0X00000000)
Offset: 0x118
Register Name: LCD0_CH0_CLK_REG
Bit
Read/
Write
Default/Hex
Description
31
R/W
0x0
SCLK_GATING.
Gating Special Clock
0: Clock is OFF
1: Clock is ON
This special clock = Clock Source
30
R/W
0x0
LCD0_RST.
LCD0 Reset.
0: reset valid, 1: reset invalid.