Allwinner A20 - Page 79

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 79 / 812
Offset: 0x118
Register Name: LCD0_CH0_CLK_REG
Bit
Read/
Write
Default/Hex
Description
29:26
/
/
/
25:24
R/W
0x0
CLK_SRC_SEL.
Clock Source Select
00: PLL3(1X)
01: PLL7(1X)
10: PLL3(2X)
11: PLL6*2
23:0
/
/
/
1.5.4.50. LCD 1 CH0 CLOCK(DEFAULT: 0X00000000)
Offset: 0x11C
Register Name: LCD1_CH0_CLK_REG
Bit
Read/
Write
Default/Hex
Description
31
R/W
0x0
SCLK_GATING.
Gating Special Clock
0: Clock is OFF
1: Clock is ON
This special clock = Clock Source
30
R/W
0x0
LCD1_RST.
LCD1 Reset.
0: reset valid, 1: reset invalid.
29:26
/
/
/
25:24
R/W
0x0
CLK_SRC_SEL.
Clock Source Select
00: PLL3(1X)
01: PLL7(1X)
10: PLL3(2X)
11: PLL7(2X)
23:0
/
/
/