Allwinner A20 - Page 80

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 80 / 812
1.5.4.51. CSI SPECIAL CLOCK REGITSTER(DEFAULT: 0X00000000)
Offset: 0x120
Register Name: CSI_SCLK_REG
Bit
Read/
Write
Default/Hex
Description
31
R/W
0x0
SCLK_GATING.
Gating Special Clock
0: Clock is OFF
1: Clock is ON
This special clock = Clock Source/Divider M.
30:26
/
/
/
25:24
R/W
0x0
SCLK2_SRC_SEL.
Special Clock 2 Source Select
00: PLL3(1X)
01: PLL4
10: PLL5
11: PLL6
23:4
/
/
/
3:0
R/W
0x0
CLK_DIV_RATIO_M.
Clock divide ratio (m)
The pre-divided clock is divided by (m+1). The divider is from
1 to 16.
1.5.4.52. TVD CLOCK(DEFAULT: 0X00000000)
Offset: 0x128
Register Name: TVD_CLK_REG
Bit
Read/
Write
Default/Hex
Description
31
R/W
0x0
SCLK2_GATING.
Gating Special Clock 2
0: Clock is OFF
1: Clock is ON
This special clock = Clock Source/ CLK_DIV_RATIO1_M.
Gating Special Clock 1 should be ON at the same time.
30:20
/
/
/
19:16
R/W
0x0
CLK_DIV_RATIO2_M.