Allwinner A20 - Page 81

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 81 / 812
Clock divide ratio (m)
The pre-divided clock is divided by (m+1). The divider is from
1 to 16.
15
R/W
0x0
SCLK1_GATING.
Gating Special Clock 1
0: Clock is OFF
1: Clock is ON
This special clock =
Clock Source/ CLK_DIV_RATIO1_M/CLK_DIV_RATIO2_M.
14:9
/
/
/
8
R/W
0x0
CLK1_SRC_SEL.
Clock Source Select
0: PLL3
1: PLL7
7:4
/
/
/
3:0
R/W
0x0
CLK_DIV_RATIO1_M.
Clock divide ratio (m)
The pre-divided clock is divided by (m+1). The divider is from
1 to 16.
1.5.4.53. LCD 0 CH1 CLOCK(DEFAULT: 0X00000000)
Offset: 0x12C
Register Name: LCD0_CH1_CLK_REG
Bit
Read/
Write
Default/Hex
Description
31
R/W
0x0
SCLK2_GATING.
Gating Special Clock 2
0: Clock is OFF
1: Clock is ON
This special clock 2= Special Clock 2 Source/Divider M.
30:26
/
/
/
25:24
R/W
0x0
SCLK2_SEL.
Special Clock 2 Source Select
00: PLL3(1X)
01: PLL7(1X)
10: PLL3(2X)
11: PLL7(2X)