Allwinner A20 - Page 801

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 801 / 812
6.16.5.24. CAN ACCEPTANCE CODE REGISTER (RESET MODE)
Offset: 0x40
Register Name:
CAN_AC0_REG
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
31:0
R/W
0
CAN_ACP_CODE
CAN acceptance code byte[3:0]
6.16.5.25. CAN ACCEPTANCE MASK REGISTER (RESET MODE)
Offset: 0x44
Register Name:
CAN_AM0_REG
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
31:8
/
/
reserved
7:0
R/W
0
CAN_ACP_MSK
CAN acceptance mask byte[3:0]
6.16.5.26. CAN TX MESSAGE BUFFER FOR READ REGISTER
Offset: 0x180~0X1B0
Register Name:
CAN_WBUF_RD
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
31:8
/
/
/
7:0
R
0
TBUF_RD_BACK
TX message buffer for read back.
Each register is 32-bit width register, but only the lower 8 bits
are valid to access. All higher 24 bits will return 0 when be
read.