Allwinner A20 - Page 84

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 84 / 812
Offset: 0x134
Register Name: CSI0_CLK_REG
Bit
Read/
Write
Default/Hex
Description
000: OSC24M
001: PLL3(1X)
010: PLL7(1X)
011: /
100: /
101: PLL3(2X)
110: PLL7(2X)
111: /
23:5
/
/
/
4:0
/
/
CLK_DIV_RATIO_M.
Clock divide ratio (m)
The pre-divided clock is divided by (m+1). The divider is from
1 to 32.
1.5.4.56. CSI 1 CLOCK(DEFAULT: 0X00000000)
Offset: 0x138
Register Name: CSI1_CLK_REG
Bit
Read/
Write
Default/Hex
Description
31
R/W
0x0
SCLK_GATING.
Gating Special Clock
0: Clock is OFF
1: Clock is ON
This special clock = Clock Source/Divider M.
30
R/W
0x0
CSI1_RST.
CSI1 Reset.
0: reset valid, 1: reset invalid.
29:27
/
/
/
26:24
R/W
0x0
Clock Source Select
000: OSC24M
001: PLL3(1X)
010: PLL7(1X)
011: /
100: /