Allwinner A20 - Page 85

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 85 / 812
Offset: 0x138
Register Name: CSI1_CLK_REG
Bit
Read/
Write
Default/Hex
Description
101: PLL3(2X)
110: PLL7(2X)
111: /
23:5
/
/
/
4:0
R/W
0x0
CLK_DIV_RATIO_M.
Clock divide ratio (m)
The pre-divided clock is divided by (m+1). The divider is from
1 to 32.
1.5.4.57. VE CLOCK(DEFAULT: 0X00000000)
Offset: 0x13C
Register Name: VE_CLK_REG
Bit
Read/
Write
Default/Hex
Description
31
R/W
0x0
SCLK_GATING.
Gating the Special clock for VE(0: mask, 1: pass).
Its clock source is the PLL4 output.
This special clock = Clock Source/Divider N.
30:19
/
/
/.
18:16
R/W
0x0
CLK_DIV_RATIO_N.
Clock pre-divide ratio (N)
The select clock source is pre-divided by n+1. The divider is
from 1 to 8.
15:1
/
/
/
0
R/W
0x0
VE_RST.
VE Reset.
0: reset valid, 1: reset invalid.
1.5.4.58. AUDIO CODEC CLOCK(DEFAULT: 0X00000000)
Offset: 0x140
Register Name: AUDIO_CODEC_CLK_REG
Bit
Read/
Write
Default/Hex
Description