Allwinner A20 - Page 86

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 86 / 812
Offset: 0x140
Register Name: AUDIO_CODEC_CLK_REG
Bit
Read/
Write
Default/Hex
Description
31
R/W
0x0
SCLK_GATING.
Gating Special Clock
0: Clock is OFF
1: Clock is ON
This special clock = PLL2 output.
30:0
/
/
/
1.5.4.59. AVS CLOCK(DEFAULT: 0X00000000)
Offset: 0x144
Register Name: AVS_CLK_REG
Bit
Read/
Write
Default/Hex
Description
31
R/W
0x0
SCLK_GATING.
Gating Special Clock
0: Clock is OFF
1: Clock is ON
This special clock = OSC24M.
30:0
/
/
/
1.5.4.60. ACE CLOCK(DEFAULT: 0X00000000)
Offset: 0x148
Register Name: ACE_CLK_REG
Bit
Read/
Write
Default/Hex
Description
31
R/W
0x0
SCLK_GATING.
Gating Special Clock(Max Clock = 200MHz)
0: Clock is OFF
1: Clock is ON
This special clock = Clock Source/Divider M.
30:25
/
/
/
24
R/W
0x0
CLK_SRC_SEL.
Clock Source Select
0: PLL4