Allwinner A20 - Page 87

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 87 / 812
Offset: 0x148
Register Name: ACE_CLK_REG
Bit
Read/
Write
Default/Hex
Description
1: PLL5
23:17
/
/
/
16
R/W
0x0
ACE_RST.
ACE Reset.
0: reset valid, 1: reset invalid
15:4
/
/
/.
3:0
R/W
0x0
CLK_DIV_RATIO_M.
Clock divide ratio (m)
The pre-divided clock is divided by (m+1). The divider is from 1
to 16.
1.5.4.61. LVDS CLOCK(DEFAULT: 0X00000000)
Offset: 0x14C
Register Name:LVDS_CLK_REG
Bit
Read/
Write
Default/Hex
Description
31:1
/
/
/.
0
R/W
0x0
LVDS_RST.
LVDS reset.
0: reset valid, 1: reset invalid.
1.5.4.62. HDMI CLOCK(DEFAULT: 0X00000000)
Offset: 0x150
Register Name: HDMI_CLK_REG.
Bit
Read/
Write
Default/Hex
Description
31
R/W
0x0
SCLK_GATING.
Gating Special Clock
0: Clock is OFF
1: Clock is ON
This special clock = Clock Source/ Divider M
30:26
/
/
/
25:24
R/W
0x0
CLK_SRC_SEL.