Allwinner A20 - Page 88

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 88 / 812
Offset: 0x150
Register Name: HDMI_CLK_REG.
Bit
Read/
Write
Default/Hex
Description
Clock Source Select
00: PLL3(1X)
01: PLL7(1X)
10: PLL3(2X)
11: PLL7(2X)
23:4
/
/
/
3:0
R/W
0x0
CLK_DIV_RATIO_M.
Clock divide ratio (m)
The pre-divided clock is divided by (m+1). The divider is from
1 to 16.
1.5.4.63. MALI400 CLOCK(DEFAULT: 0X00000000)
Offset: 0x154
Register Name: MALI400_CLK_REG
Bit
Read/W
rite
Default/Hex
Description
31
R/W
0x0
SCLK_GATING.
Gating Special Clock(Max Clock = 381MHz)
0: Clock is OFF
1: Clock is ON
This special clock = Clock Source/Divider M.
30
R/W
0x0
MALI400_RST.
Mali400 Reset.
0: reset valid, 1: reset invalid
29:27
/
/
/
26:24
R/W
0x0
CLK_SRC_SEL.
Clock Source Select
000: PLL3
001: PLL4
010: PLL5
011: PLL7
100: PLL8
101:/
110:/