Allwinner A20 - Page 89

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 89 / 812
Offset: 0x154
Register Name: MALI400_CLK_REG
Bit
Read/W
rite
Default/Hex
Description
111:/
23:4
/
/
/
3:0
R/W
0x0
CLK_DIV_RATIO_M.
Clock divide ratio (m)
The pre-divided clock is divided by (m+1). The divider is from
1 to 16.
1.5.4.64. MBUS CLOCK CONTROL(DEFAULT: 0X00000000)
Offset: 0x15C
Register Name: MBUS_SCLK_CFG_REG
Bit
Read/
Write
Default/Hex
Description
31
R/W
0x0
MBUS_SCLK_GATING.
Gating Clock for MBUS
0: Clock is OFF,
1: Clock is ON;
MBUS_CLOCK = Clock Source/Divider N/Divider M
30:26
/
/
/
25:24
R/W
0x0
MBUS_SCLK_SRC
Clock Source Select
00: OSC24M
01: PLL6*2
10: PLL5
11: Reserved
23:18
/
/
/
17:16
R/W
0x0
MBUS_SCLK_RATIO_N
Clock Pre-divide Ratio (N)
The select clock source is pre-divided by 2^N. The divider is
1/2/4/8.
15:4
/
/
/
3:0
R/W
0x0
MBUS_SCLK_RATIO_M
Clock Divide Ratio (M)
The divided clock is divided by (M+1). The divider is from 1 to
16.