Allwinner A20 - Page 90

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 90 / 812
1.5.4.65. GMAC CLOCK REGISTER (DEFAULT: 0X00000000)
Offset: 0x164
Register Name: GMAC_CLK_REG
Bit
Read/
Write
Default/Hex
Description
31:10
/
/
/
9:8
R/W
0x0
TXC_DIV_CFG
Clock pre-divide ratio(n)
External transmit clock (125MHz) is pre-divided by as follows
for RGMII.
00:/1, generate 125MHz;
01:/5,generate 25 MHz;
10: /50,generate 2.5 MHz
11: Reserved
7:5
R/W
0x0
GRXDC
Configure GMAC Receive Clock Delay Chian.
000:
001:
…
111:
4
R/W
0x0
GRXIE
Enable GMAC Receive Clock Invertor.
0: Disable;
1: Enable;
3
R/W
0x0
GTXIE
Enable GMAC Transmit Clock Invertor.
0: Disable;
1: Enable;
2
R/W
0x0
GPIT
GMAC PHY Interface Type
0: MII;
1: RGMII;
1:0
R/W
0x0
GTCS
GMAC Transmit Clock Source
00: Transmit clock source for MII;
01: External transmit clock source(125MHz) for RGMII;