Allwinner A20 - Page 91

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 91 / 812
Offset: 0x164
Register Name: GMAC_CLK_REG
Bit
Read/
Write
Default/Hex
Description
10: Internal transmit clock source for RGMII;
11: Reserved;
1.5.4.66. HDMI1 RESET REGISTER (DEFAULT: 0X00000000)
Offset: 0x170
Register Name: HDMI1_RST_REG
Bit
Read/
Write
Default/Hex
Description
31:3
/
/
/
2
R/W
0x0
AUDIO_DMA_RST
Audio_dma reset.
0: assert.
1:de-assert.
1
R/W
0x0
SYSRST.
HDMI1 system reset
0: assert.
1:de-assert.
0
R/W
0x0
HRST
hreset
0: assert.
1:de-assert.
1.5.4.67. HDMI1 CONTROL REGISTER (DEFAULT: 0X00000000)
Offset: 0x174
Register Name: HDMI1_CTRL_REG
Bit
Read/
Write
Default/Hex
Description
31:0
R/W
0x0
HDMI1 System Control Register
1.5.4.68. HDMI1 SLOW CLOCK REGISTER (DEFAULT: 0X00000000)
Offset: 0x178
Register Name: HDMI1_SLOW_CLK_REG