Allwinner A20 - Page 92

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 92 / 812
Bit
Read/
Write
Default/Hex
Description
31
R/W
0x0
SCLK_GATING.
Gating Special Clock
0: Clock is OFF
1: Clock is ON
This special clock is OSC24M.
30:0
/
/
/
1.5.4.69. HDMI1 REPEAT CLOCK REGISTER (DEFAULT: 0X00000000)
Offset: 0x17C
Register Name: HDMI1_REPEAT_CLK_REG
Bit
Read/
Write
Default/Hex
Description
31
R/W
0x0
SCLK_GATING.
Gating Special Clock
0: Clock is OFF
1: Clock is ON
This special clock = Clock source/Divider M.
30:26
/
/
/
25:24
R/W
0x0
CLK_SRC_SEL.
Clock Source Select
00: PLL3(1X)
01: PLL7(1X)
10:/
11:/
23:4
/
/
/
3:0
R/W
0x0
CLK_DIV_RATIO_M.
Clock divide ratio (m)
The pre-divided clock is divided by (m+1). The divider is from 1
to 16.
1.5.4.70. CLK_OUTA_REG (DEFAULT: 0X00000000)
Offset: 0x1F0
Register Name: CLK_OUTA_REG
Bit
Read/
Write
Default/Hex
Description