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ARM Cortex-A53 MPCore
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System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-41
ID021414 Non-Confidential
Table 4-49 shows the ID_AA64ISAR0_EL1 bit assignments.
To access the ID_AA64ISAR0_EL1:
MRS <Xt>, ID_AA64ISAR0_EL1 ; Read ID_AA64ISAR0_EL1 into Xt
Register access is encoded as follows:
4.3.21 AArch64 Memory Model Feature Register 0, EL1
The ID_AA64MMFR0_EL1 characteristics are:
Purpose Provides information about the implemented memory model and memory
management support in the AArch64 Execution state.
Usage constraints This register is accessible as follows:
Table 4-49 ID_AA64ISAR0_EL1 bit assignments
Bits Name Function
[63:20] - Reserved,
RES0.
[19:16] CRC32
0x1
CRC32 instructions are implemented.
[15:12] SHA2 Indicates whether
SHA2
instructions are implemented. The possible values are:
0b0000
No
SHA2
instructions implemented. This is the value if the implementation does not include the
Cryptography Extension, or if it is disabled.
0b0001
SHA256H
,
SHA256H2
,
SHA256U0
, and
SHA256U1
implemented. This is the value if the implementation
includes the Cryptography Extension.
All other values reserved.
[11:8] SHA1 Indicates whether
SHA1
instructions are implemented. The possible values are:
0b0000
No
SHA1
instructions implemented. This is the value if the implementation does not include the
Cryptography Extension.
0b0001
SHA1C
,
SHA1P
,
SHA1M
,
SHA1SU0
, and
SHA1SU1
implemented. This is the value if the implementation
includes the Cryptography Extension.
All other values reserved.
[7:4] AES Indicates whether
AES
instructions are implemented. The possible values are:
0b0000
No
AES
instructions implemented. This is the value if the implementation does not include the
Cryptography Extension.
0b0010
AESE
,
AESD
,
AESMC
, and
AESIMC
implemented, plus
PMULL
and
PMULL2
instructions operating on 64-bit
data. This is the value if the implementation includes the Cryptography Extension.
All other values reserved.
[3:0] - Reserved,
RES0.
Table 4-50 ID_AA64ISAR0_EL1 access encoding
op0 op1 CRn CRm op2
11 000 0000 0110 000
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
-RORORORO RO

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