System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-42
ID021414 Non-Confidential
Configurations ID_AA64MMFR0_EL1 is architecturally mapped to external register
ID_AA64MMFR0_EL1.
Attributes ID_AA64MMFR0_EL1 is a 64-bit register.
Figure 4-20 shows the ID_AA64MMFR0_EL1 bit assignments.
Figure 4-20 ID_AA64MMFR0_EL1 bit assignments
Table 4-51 shows the ID_AA64MMFR0_EL1 bit assignments.
To access the ID_AA64MMFR0_EL1:
MRS <Xt>, ID_AA64MMFR0_EL1 ; Read ID_AA64MMFR0_EL1 into Xt
Register access is encoded as follows:
Table 4-51 ID_AA64MMFR0_EL1 bit assignments
Bits Name Function
[63:32] - Reserved,
RES0.
[31:28] TGran4 Support for 4 KB memory translation granule size:
0x0
Indicates that the 4KB granule is supported.
[27:24] TGran64 Support for 64 KB memory translation granule size:
0x0
Indicates that the 64KB granule is supported.
[23:20] TGran16 Support for 16 KB memory translation granule size:
0x0
Indicates that the 16KB granule is not supported.
[19:16] BigEndEL0 Mixed-endian support only at EL0.
RES0
[15:12] SNSMem Secure versus Non-secure Memory distinction:
0b0001
Supports a distinction between Secure and Non-secure Memory.
[11:8] BigEnd Mixed-endian configuration support:
0b0001
Mixed-endian support. The SCTLR_ELx.EE and SCTLR_EL1.E0E bits are RW.
[7:4] ASIDBits Number of ASID bits:
0b0010
16 bits.
[3:0] PARange Physical address range supported:
0b0010
40 bits, 1 TB.
Table 4-52 ID_AA64MMFR0_EL1 access encoding
op0 op1 CRn CRm op2
11 000 0000 0111 000
To Next Page
Loading...
