System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-43
ID021414 Non-Confidential
4.3.22 Cache Size ID Register
The CCSIDR_EL1 characteristics are:
Purpose Provides information about the architecture of the caches.
Usage constraints This register is accessible as follows:
Configurations CCSIDR_EL1 is architecturally mapped to AArch32 register CCSIDR.
See Cache Size ID Register on page 4-183.
Attributes CCSIDR_EL1 is a 32-bit register.
Figure 4-21 shows the CCSIDR_EL1 bit assignments.
Figure 4-21 CCSIDR_EL1 bit assignments
Table 4-53 shows the CCSIDR_EL1 bit assignments.
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
-RORORORO RO
Table 4-53 CCSIDR_EL1 bit assignments
Bits Name Function
[31] WT Indicates support for write-through:
0
Cache level does not support write-through.
[30] WB Indicates support for write-back:
0
Cache level does not support write-back.
1
Cache level supports write-back.
[29] RA Indicates support for Read-Allocation:
0
Cache level does not support Read-Allocation.
1
Cache level supports Read-Allocation.
[28] WA Indicates support for Write-Allocation:
0
Cache level does not support Write-Allocation.
1
Cache level supports Write-Allocation.
[27:13]
NumSets
a
Indicates the number of sets in cache - 1. Therefore, a value of 0 indicates 1 set in the cache. The number
of sets does not have to be a power of 2.
[12:3]
Associativity
a
Indicates the associativity of cache - 1. Therefore, a value of 0 indicates an associativity of 1. The
associativity does not have to be a power of 2.
[2:0]
LineSize
a
Indicates the (log
2
(number of words in cache line)) - 2:
0b010
16 words per line.
a. For more information about encoding, see Table 4-181 on page 4-185.
To Next Page
Loading...
