System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-44
ID021414 Non-Confidential
Table 4-181 on page 4-185 shows the individual bit field and complete register encodings for
the CCSIDR_EL1. The CSSELR determines which CCSIDR_EL1 to select.
To access the CCSIDR_EL1:
MRS <Xt>, CCSIDR_EL1 ; Read CCSIDR_EL1 into Xt
Register access is encoded as follows:
4.3.23 Cache Level ID Register
The CLIDR_EL1 characteristics are:
Purpose Identifies:
• The type of cache, or caches, implemented at each level.
• The Level of Coherency and Level of Unification for the cache
hierarchy.
Usage constraints This register is accessible as follows:
Configurations CLIDR_EL1 is architecturally mapped to AArch32 register CLIDR. See
Cache Level ID Register on page 4-185.
Attributes CLIDR_EL1 is a 32-bit register.
Figure 4-22 shows the CLIDR_EL1 bit assignments.
Figure 4-22 CLIDR_EL1 bit assignments
Table 4-54 CCSIDR_EL1 access encoding
op0 op1 CRn CRm op2
11 001 0000 0000 000
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
-RORORORO RO
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