System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-55
ID021414 Non-Confidential
To access the SCTLR_EL1:
MRS <Xt>, SCTLR_EL1 ; Read SCTLR_EL1 into Xt
MSR SCTLR_EL1, <Xt> ; Write Xt to SCTLR_EL1
4.3.31 Auxiliary Control Register, EL1
The processor does not implement the ACTLR_EL1 register. This register is always
RES0.
4.3.32 Auxiliary Control Register, EL2
The ACTLR_EL2 characteristics are:
Purpose Controls write access to
IMPLEMENTATION DEFINED registers in
Non-secure EL1 modes, such as CPUACTLR, CPUECTLR, L2CTLR,
L2ECTLR and L2ACTLR.
Usage constraints This register is accessible as follows:
Configurations The ACTLR_EL2 is architecturally mapped to the AArch32 HACTLR
register. See Hyp Auxiliary Control Register on page 4-205.
Attributes ACTLR_EL2 is a 32-bit register.
Figure 4-29 shows the ACTLR_EL2 bit assignments.
Figure 4-29 ACTLR_EL2 bit assignments
[0] M MMU enable. The possible values are:
0
EL1 and EL0 stage 1 MMU disabled. This is the reset value.
1
EL1 and EL0 stage 1 MMU enabled.
Table 4-67 SCTLR_EL1 bit assignments (continued)
Bits Name Function
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
-- -RWRW RW
31 0
RES
0
L2ACTLR_EL1 access control
1234567
L2ECTLR_EL1 access control
L2CTLR_EL1 access control
CPUECTLR_EL1 access control
CPUACTLR_EL1 access control
RES
0
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