System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-56
ID021414 Non-Confidential
Table 4-68 shows the ACTLR_EL2 bit assignments.
To access the ACTLR_EL2:
MRS <Xt>, ACTLR_EL2 ; Read ACTLR_EL2 into Xt
MSR ACTLR_EL2, <Xt> ; Write Xt to ACTLR_EL2
4.3.33 Auxiliary Control Register, EL3
The ACTLR_EL3 characteristics are:
Purpose Controls write access to
IMPLEMENTATION DEFINED registers in EL2, such
as CPUACTLR, CPUECTLR, L2CTLR, L2ECTLR and L2ACTLR.
Usage constraints This register is accessible as follows:
Configurations ACTLR_EL3 is mapped to AArch32 register ACTLR (S). See Auxiliary
Control Register on page 4-196.
Attributes ACTLR_EL3 is a 32-bit register.
Table 4-68 ACTLR_EL2 bit assignments
Bits Name Function
[31:7] - Reserved,
RES0.
[6] L2ACTLR access
control
L2ACTLR_EL1 write access control. The possible values are:
0
The register is not write accessible from Non-secure EL1.This is the reset value.
1
The register is write accessible from Non-secure EL1.
Write access from Non-secure EL1 also requires ACTLR_EL3[6] to be set.
[5] L2ECTLR access
control
L2ECTLR_EL1 write access control. The possible values are:
0
The register is not write accessible from Non-secure EL1.This is the reset value.
1
The register is write accessible from Non-secure EL1.
Write access from Non-secure EL1 also requires ACTLR_EL3[5] to be set.
[4] L2CTLR access control L2CTLR_EL1 write access control. The possible values are:
0
The register is not write accessible from Non-secure EL1.This is the reset value.
1
The register is write accessible from Non-secure EL1.
Write access from Non-secure EL1 also requires ACTLR_EL3[4] to be set.
[3:2] - Reserved,
RES0.
[1] CPUECTLR access
control
CPUECTLR_EL1 write access control. The possible values are:
0
The register is not write accessible from Non-secure EL1.This is the reset value.
1
The register is write accessible from Non-secure EL1.
Write access from Non-secure EL1 also requires ACTLR_EL3[1] to be set.
[0] CPUACTLR access
control
CPUACTLR_EL1 write access control. The possible values are:
0
The register is not write accessible from Non-secure EL1.This is the reset value.
1
The register is write accessible from Non-secure EL1.
Write access from Non-secure EL1 also requires ACTLR_EL3[0] to be set.
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
-- --RW RW
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