ARM Cortex-A53 MPCore - Page 118

System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-57
ID021414 Non-Confidential
Figure 4-30 shows the ACTLR_EL3 bit assignments.
Figure 4-30 ACTLR_EL3 bit assignments
Table 4-69 shows the ACTLR_EL3 bit assignments.
To access the ACTLR_EL3:
MRS <Xt>, ACTLR_EL3 ; Read ACTLR_EL3 into Xt
MSR ACTLR_EL3, <Xt> ; Write Xt to ACTLR_EL3
4.3.34 Architectural Feature Access Control Register
The CPACR_EL1 characteristics are:
Purpose Controls access to trace functionality and access to registers associated
with Advanced SIMD and Floating-point execution.
RES
0
31 765 10
RES
0
432
L2ACTLR_EL1 access control
L2ECTLR_EL1 access control
L2CTLR_EL1 access control
CPUECTLR_EL1 access control
CPUACTLR_EL1 access control
Table 4-69 ACTLR_EL3 bit assignments
Bits Name Function
[31:7] - Reserved,
RES0.
[6] L2ACTLR access control L2ACTLR_EL1 write access control. The possible values are:
0 The register is not write accessible from a lower exception level. This is
the reset value.
1 The register is write accessible from EL2.
[5] L2ECTLR access control L2ECTLR_EL1 write access control. The possible values are:
0 The register is not write accessible from a lower exception level. This is
the reset value.
1 The register is write accessible from EL2.
[4] L2CTLR access control L2CTLR_EL1 write access control. The possible values are:
0 The register is not write accessible from a lower exception level. This is
the reset value.
1 The register is write accessible from EL2.
[3:2] - Reserved,
RES0.
[1] CPUECTLR access control CPUECTLR_EL1 write access control. The possible values are:
0 The register is not write accessible from a lower exception level. This is
the reset value.
1 The register is write accessible from EL2.
[0] CPUACTLR access control CPUACTLR_EL1 write access control. The possible values are:
0 The register is not write accessible from a lower exception level. This is
the reset value.
1 The register is write accessible from EL2.