System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-58
ID021414 Non-Confidential
CPACR_EL1 is part of the Other system registers functional group.
Usage constraints This register is accessible as follows:
Configurations CPACR_EL1 is architecturally mapped to AArch32 register CPACR. See
Architectural Feature Access Control Register on page 4-197.
Attributes CPACR_EL1 is a 32-bit register.
Figure 4-31 shows the CPACR_EL1 bit assignments.
Figure 4-31 CPACR_EL1 bit assignments
Table 4-70 shows the CPACR_EL1 bit assignments.
To access the CPACR_EL1:
MRS <Xt>, CPACR_EL1 ; Read CPACR_EL1 into Xt
MSR CPACR_EL1, <Xt> ; Write Xt to CPACR_EL1
4.3.35 System Control Register, EL2
The SCTLR_EL2 characteristics are:
Purpose Provides top level control of the system, including its memory system at
EL2.
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
-RWRWRWRW RW
Table 4-70 CPACR_EL1 bit assignments
Bits Name Function
[31:29] - Reserved,
RES0.
[28] TTA Causes access to the Trace functionality to trap to EL1 when executed from EL0 or EL1.
This bit is
RES0.
[27:22] - Reserved,
RES0.
[21:20] FPEN Traps instructions that access registers associated with Advanced SIMD and Floating-point execution to trap to
EL1 when executed from EL0 or EL1. The possible values are:
0bX0
Trap any instruction in EL0 or EL1 that uses registers associated with Advanced SIMD and
Floating-point execution. The reset value is
0b00
.
0b01
Trap any instruction in EL0 that uses registers associated with Advanced SIMD and
Floating-point execution. Instructions in EL1 are not trapped.
0b11
No instructions are trapped.
This field is RES0 if Advanced SIMD and Floating-point are not implemented.
[19:0] - Reserved,
RES0.
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