ARM Cortex-A53 MPCore - Page 120

System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-59
ID021414 Non-Confidential
SCTLR_EL2 is part of:
• The Virtual memory control registers functional group.
• The Hypervisor and virtualization registers functional group.
Usage constraints This register is accessible as follows:
Configurations SCTLR_EL2 is architecturally mapped to AArch32 register HSCTLR.
See Hyp System Control Register on page 4-207.
Attributes SCTLR_EL2 is a 32-bit register.
Figure 4-32 shows the SCTLR_EL2 bit assignments.
Figure 4-32 SCTLR_EL2 bit assignments
Table 4-71 shows the SCTLR_EL2 bit assignments.
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
-- -RWRW RW
31 0
EE
2526 20
RES
1
19 18 12 11
2143
WXN
ICAM
SA
RES
0
30 29 28 27
RES
1
RES
0
24 23
RES 0
22 21
RES
0
17 16 15 14 13
RES1
RES
0
RES 1
RES 0
10 6 5
RES
0
RES
1
RES 1
Table 4-71 SCTLR_EL2 bit assignments
Bits Name Function
[31:30] - Reserved,
RES0.
[29:28] - Reserved,
RES1.
[27:26] - Reserved,
RES0.
[25] EE Exception endianness. The possible values are:
0 Little endian.
1 Big endian.
The reset value depends on the value of the CFGEND configuration input.
[24] - Reserved,
RES0.
[23:22] - Reserved,
RES1.
[21:20] - Reserved,
RES0.
[19] WXN Force treatment of all memory regions with write permissions as XN. The possible values are:
0 Regions with write permissions are not forced XN. This is the reset value.
1 Regions with write permissions are forced XN.
[18] - Reserved,
RES1.
[17] - Reserved,
RES0.