System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-60
ID021414 Non-Confidential
To access the SCTLR_EL2:
MRS <Xt>, SCTLR_EL2 ; Read SCTLR_EL2 into Xt
MSR SCTLR_EL2, <Xt> ; Write Xt to SCTLR_EL2
4.3.36 Hypervisor Configuration Register
The HCR_EL2 characteristics are:
Purpose Provides configuration control for virtualization, including whether
various Non-secure operations are trapped to EL2.
HCR_EL2 is part of the Hypervisor and virtualization registers functional
group.
Usage constraints This register is accessible as follows:
Configurations HCR_EL2[31:0] is architecturally mapped to AArch32 register HCR. See
Hyp Configuration Register on page 4-211.
[16] - Reserved, RES1.
[15:13] - Reserved,
RES0.
[12] I Instruction cache enable. The possible values are:
0
Instruction caches disabled. This is the reset value.
1
Instruction caches enabled.
[11] - Reserved,
RES1.
[10:6] - Reserved,
RES0.
[5:4] - Reserved,
RES1.
[3] SA Enables stack alignment check. The possible values are:
0
Disables stack alignment check.
1
Enables stack alignment check. This is the reset value.
[2] C Global enable for data and unifies caches. The possible values are:
0
Disables data and unified caches. This is the reset value.
1
Enables data and unified caches.
[1] A Enable alignment fault check The possible values are:
0
Disables alignment fault checking. This is the reset value.
1
Enables alignment fault checking.
[0] M Global enable for the EL2 MMU. The possible values are:
0
Disables EL2 MMU. This is the reset value.
1
Enables EL2 MMU.
Table 4-71 SCTLR_EL2 bit assignments (continued)
Bits Name Function
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
-- -RWRW RW
To Next Page
Loading...
