System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-62
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Table 4-72 shows the HCR_EL2 bit assignments.
Table 4-72 HCR_EL2 bit assignments
Bits Name Function
[63:34] - Reserved,
RES0.
[33] ID Disables stage 2 instruction cache. When HCR_EL2.VM is 1, this forces all stage 2 translations for instruction
accesses to Normal memory to be Non-cacheable for the EL1/EL0 translation regimes. The possible values are:
0
Has no effect on stage 2 EL1/EL0 translation regime for instruction accesses. This is the reset
value.
1
Forces all stage 2 translations for instruction accesses to Normal memory to be Non-cacheable
for the EL1/EL0 translation regime.
[32] CD Disables stage 2 data cache. When HCR_EL2.VM is 1, this forces all stage 2 translations for data accesses and
translation table walks to Normal memory to be Non-cacheable for the EL1/EL0 translation regimes. The
possible values are:
0
Has no effect on stage 2 EL1/EL0 translation regime for data access or translation table walks.
This is the reset value.
1
Forces all stage 2 translations for data accesses and translation table walks to Normal memory
to be Non-cacheable for the EL1/EL0 translation regime.
[31] RW Register width control for lower exception levels. The possible values are:
0
Lower levels are all AArch32. This is the reset value.
1
EL1 is AArch64. EL0 is determined by the register width described in the current processing
state when executing at EL0.
[30] TRVM
Trap reads of Virtual Memory controls.
a
The possible values are:
0
Non-secure EL1 reads are not trapped. This is the reset value.
1
Non-secure EL1 reads are trapped to EL2.
[29] HCD Reserved,
RES0.
[28] TDZ Traps DC ZVA instruction. The possible values are:
0
DC ZVA instruction is not trapped. This is the reset value.
1
DC ZVA instruction is trapped to EL2 when executed in Non-secure EL1 or EL0.
[27] TGE Traps general exceptions. If this bit is set, and SCR_EL3.NS is set, then:
• All Non-secure EL1 exceptions are routed to EL2.
• For Non-secure EL1, the SCTLR_EL1.M bit is treated as 0 regardless of its actual state other than the
purpose of reading the bit.
• The HCR_EL2.FMO, HCR_EL2.IMO, and HCR_EL2.AMO bits are treated as 1 regardless of their
actual state other than for the purpose of reading the bits.
• All virtual interrupts are disabled.
• Any implementation defined mechanisms for signaling virtual interrupts are disabled.
• An exception return to Non-secure EL1 is treated as an illegal exception return.
[26] TVM
Trap virtual memory controls.
a
The possible values are:
0
Non-secure EL1 writes are not trapped. This is the reset value.
1
Non-secure EL1 writes are trapped to EL2.
[25] TTLB
Traps TLB maintenance instructions.
a
The possible values are:
0
Non-secure EL1 TLB maintenance instructions are not trapped. This is the reset value.
1
TLB maintenance instructions executed from Non-secure EL1that are not UNDEFINED are
trapped to EL2.
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