System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-63
ID021414 Non-Confidential
[24] TPU
Traps cache maintenance instructions to Point of Unification (POU).
a
The possible values are:
0
Cache maintenance instructions are not trapped. This is the reset value.
1
Cache maintenance instructions to the POU executed from Non-secure EL1 or EL0 that are not
UNDEFINED are trapped to EL2.
[23] TPC
Traps data or unified cache maintenance instructions to Point of Coherency (POC).
a
The possible values are:
0
Data or unified cache maintenance instructions are not trapped. This is the reset value.
1
Data or unified cache maintenance instructions by address to the POC executed from
Non-secure EL1 or EL0 that are not UNDEFINED are trapped to EL2.
[22] TSW
Traps data or unified cache maintenance instructions by Set or Way.
a
The possible values are:
0
Data or unified cache maintenance instructions are not trapped. This is the reset value.
1
Data or unified cache maintenance instructions by Set or Way executed from Non-secure EL1
that are not UNDEFINED are trapped to EL2.are not trapped.
[21] TACR Traps Auxiliary Control registers. The possible values are:
0
Accesses to Auxiliary Control registers are not trapped. This is the reset value.
1
Accesses to ACTLR in AArch32 state or the ACTLR_EL1 in the AArch64 state from
Non-secure EL1 are trapped to EL2.
[20] TIDCP Trap Implementation Dependent functionality. When 1, this causes accesses to the following instruction set
space executed from Non-secure EL1 to be trapped to EL2:
AArch32 All CP15
MCR
and
MRC
instructions as follows:
• CRn is 9, Opcode1 is 0 to 7, CRm is c0, c1, c2, c5, c6, c7, or c8, and Opcode2 is 0 to 7.
• CRn is 10, Opcode1 is 0 to 7, CRm is c0, c1, c4, or c8, and Opcode2 is 0 to 7.
• CRn is 11, Opcode1 is 0 to 7, CRm is c0 to c8, or c15, and Opcode2 is 0 to 7.
AArch64 Reserved control space for
IMPLEMENTATION DEFINED functionality.
Accesses from EL0 are UNDEFINED. The reset value is 0.
[19] TSC Traps
SMC
instruction. The possible values are:
0
SMC
instruction in not trapped. This is the reset value.
1
SMC
instruction executed in Non-secure EL1 is trapped to EL2 for AArch32 and AArch64
Execution states.
[18] TID3
Traps ID group 3 registers.
a
The possible values are:
0
ID group 3 register accesses are not trapped. This is the reset value.
1
Reads to ID group 3 registers executed from Non-secure EL1 are trapped to EL2.
[17] TID2
Traps ID group 2 registers.
a
The possible values are:
0
ID group 2 register accesses are not trapped. This is the reset value.
1
Reads to ID group 2 registers and writes to CSSELR and CSSELR_EL1executed from
Non-secure EL1 or EL0, if not UNDEFINED, are trapped to EL2.
[16] TID1
Traps ID group 1 registers.
a
The possible values are:
0
ID group 1 register accesses are not trapped. This is the reset value.
1
Reads to ID group 1registers executed from Non-secure EL1 are trapped to EL2.
[15] TID0
Traps ID group 0 registers.
a
The possible values are:
0
ID group 0 register accesses are not trapped. This is the reset value.
1
Reads to ID group 0 registers executed from Non-secure EL1 are trapped to EL2.
Table 4-72 HCR_EL2 bit assignments (continued)
Bits Name Function
To Next Page
Loading...
