System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-65
ID021414 Non-Confidential
[9] FB
Forces broadcast.
b
The possible values are:
0
Instructions are not broadcast. This is the reset value.
1
Forces instruction broadcast within Inner Shareable domain when executing from Non-secure
EL1.
[8] VSE Virtual System Error/Asynchronous Abort. The possible values are:
0
Virtual System Error/Asynchronous Abort is not pending by this mechanism. This is the reset
value.
1
Virtual System Error/Asynchronous Abort is pending by this mechanism.
The virtual System Error/Asynchronous Abort is enabled only when the HCR_EL2.AMO bit is set.
[7] VI Virtual IRQ interrupt. The possible values are:
0
Virtual IRQ is not pending by this mechanism. This is the reset value.
1
Virtual IRQ is pending by this mechanism.
The virtual IRQ is enabled only when the HCR_EL2.IMO bit is set.
[6] VF Virtual FIQ interrupt. The possible values are:
0
Virtual FIQ is not pending by this mechanism. This is the reset value.
1
Virtual FIQ is pending by this mechanism.
The virtual FIQ is enabled only when the HCR_EL2.FMO bit is set.
[5] AMO Asynchronous abort and error interrupt routing. The possible values are:
0
Asynchronous external Aborts and SError Interrupts while executing at exception levels lower
than EL2 are not taken at EL2. Virtual System Error/Asynchronous Abort is disabled. This is the
reset value.
1
Asynchronous external Aborts and SError Interrupts while executing at EL2 or lower are taken
in EL2 unless routed by SCTLR_EL3.EA bit to EL3. Virtual System Error/Asynchronous Abort
is enabled.
[4] IMO Physical IRQ routing. The possible values are:
0
Physical IRQ while executing at exception levels lower than EL2 are not taken at EL2. Virtual
IRQ interrupt is disabled. This is the reset value.
1
Physical IRQ while executing at EL2 or lower are taken in EL2 unless routed by
SCTLR_EL3.IRQ bit to EL3. Virtual IRQ interrupt is enabled.
[3] FMO Physical FIQ routing. The possible values are:
0
Physical FIQ while executing at exception levels lower than EL2 are not taken at EL2. Virtual
FIQ interrupt is disabled. This is the reset value.
1
Physical FIQ while executing at EL2 or lower are taken in EL2 unless routed by
SCTLR_EL3.FIQ bit to EL3. Virtual FIQ interrupt is enabled.
[2] PTW Protected Table Walk. When this bit is set, if the stage 2 translation of a translation table access, made as part
of a stage 1 translation table walk at EL0 or EL1, maps to Device memory, the access is faulted as a stage 2
Permission fault. The reset value is
0
.
[1] SWIO Set/Way Invalidation Override. Non-secure EL1 execution of the data cache invalidate by set/way instruction is
treated as data cache clean and invalidate by set/way. When this bit is set:
• DCISW is treated as DCCISW when in the AArch32 Execution state.
• DC ISW is treated as DC CISW when in the AArch64 Execution state.
This bit is
RES1.
[0] VM Enables second stage of translation. The possible values are:
0
Disables second stage translation. This is the reset value.
1
Enables second stage translation for execution in Non-secure EL1 and EL0.
Table 4-72 HCR_EL2 bit assignments (continued)
Bits Name Function
To Next Page
Loading...
