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ARM Cortex-A53 MPCore
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System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-66
ID021414 Non-Confidential
To access the HCR_EL2:
MRS <Xt>, HCR_EL2 ; Read HCR_EL2 into Xt
MSR HCR_EL2, <Xt> ; Write Xt to HCR_EL2
4.3.37 Hyp Debug Control Register
The MDCR_EL2 characteristics are:
Purpose Controls the trapping to Hyp mode of Non-secure accesses, at EL1 or
lower, to functions provided by the debug and trace architectures and the
Performance Monitor.
Usage constraints This register is accessible as follows:
Configurations MDCR_EL2 is architecturally mapped to AArch32 register HDCR.
See Hyp Debug Control Register on page 4-217.
This register is accessible only at EL2 or EL3.
Attributes MDCR_EL2 is a 32-bit register.
Figure 4-34 shows the MDCR_EL2 bit assignments.
Figure 4-34 MDCR_EL2 bit assignments
a. See the ARM
®
Architecture Reference Manual ARMv8, for ARMv8-A architecture profile for the registers covered by this setting.
b. See the ARM
®
Architecture Reference Manual ARMv8, for ARMv8-A architecture profile for the instructions covered by this setting.
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - - RW RW RW
31 1110987654 0
RES
0 HPMN
TDOSA
TDA
TDE
HPME
TPM
TPMCR
12
TDRA

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