System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-69
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To access the MDCR_EL2:
MRS <Xt>, MDCR_EL2 ; Read MDCR_EL2 into Xt
MSR MDCR_EL2, <Xt> ; Write Xt to MDCR_EL2
4.3.38 Architectural Feature Trap Register, EL2
The CPTR_EL2 characteristics are:
Purpose Controls trapping to EL2 for accesses to CPACR, Trace functionality and
registers associated with Advanced SIMD and Floating-point execution.
Controls EL2 access to this functionality.
Usage constraints This register is accessible as follows:
Configurations CPTR_EL2 is architecturally mapped to AArch32 register HCPTR. See
Hyp Architectural Feature Trap Register on page 4-221.
Attributes CPTR_EL2 is a 32-bit register.
Figure 4-35 on page 4-70 shows the CPTR_EL2 bit assignments.
[5] TPMCR Trap PMCR_EL0 accesses:
0
Has no effect on PMCR_EL0 accesses.
1
Trap Non-secure EL0 and EL1 accesses to PMCR_EL0 to EL2.
This bit resets to 0.
See the ARM
®
Architecture Reference Manual ARMv8, for ARMv8-A architecture profile for more information.
[4:0] HPMN Hyp Performance Monitor count. Defines the number of Performance Monitors counters that are accessible
from Non-secure EL1 and EL0 modes.
In Non-secure state, HPMN divides the Performance Monitors counters as follows. For counter
n
in Non-secure
state:
For example, If PMnEVCNTR is performance monitor counter n then, in Non-secure state:
• If n is in the range 0 ≤ n < HPMN, the counter is accessible from EL1 and EL2, and from EL0 if permitted
by PMUSERENR_EL0. PMCR_EL0.E enables the operation of counters in this range.
• If n is in the range HPMN ≤ n < 6
a
, the counter is accessible only from EL2. MDCR_EL2.HPME enables
the operation of counters in this range.
If the field is set to 0, then non-secure EL0 or EL1 has no access to any counters.
If the field is set to a value greater than six, the behavior is the same as if the value is six.
For reads of MDCR_EL2.HPMN by EL2 or higher, if this field is set to 0 or to a value larger than
PMCR_EL0.N, the processor returns the value that was written to MDCR_EL2.HPMN.
This field resets to
0x6
.
a. There are six performance counters, specified by PMCR.N.
Table 4-73 MDCR_EL2 bit assignments (continued)
Bits Name Function
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
-- -RWRW RW
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