ARM Cortex-A53 MPCore - Page 131

System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-70
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Figure 4-35 CPTR_EL2 bit assignments
Table 4-74 shows the CPTR_EL2 bit assignments.
To access the CPTR_EL2:
MRS <Xt>, CPTR_EL2 ; Read CPTR_EL2 into Xt
MSR CPTR_EL2, <Xt> ; Write Xt to CPTR_EL2
4.3.39 Hyp System Trap Register
The HSTR_EL2 characteristics are:
Purpose Controls access to ThumbEE and coprocessor registers at lower exception
levels in AArch32.
Usage constraints This register is accessible as follows:
Configurations HSTR_EL2 is architecturally mapped to AArch32 register HSTR. See
Hyp System Trap Register on page 4-236.
31 0
RES0 RES1
TFPTCPAC
20 1921 10 911
RES0
TTA
13 1214
RES1
RES0
30
Table 4-74 CPTR_EL2 bit assignments
Bits Name Function
[31] TCPAC Traps direct access to CPACR from Non-secure EL1 to EL2. The possible values are:
0 Access to CPACR is not trapped. This is the reset value.
1 Access to CPACR is trapped.
[30:21] - Reserved,
RES0.
[20] TTA Trap Trace Access.
Not implemented.
RES0.
[19:14] - Reserved,
RES0.
[13:12] - Reserved,
RES1.
[11] - Reserved,
RES0.
[10] TFP Traps instructions that access registers associated with Advanced SIMD and Floating-point execution from a
lower exception level to EL2, unless trapped to EL1. The possible values are:
0 Instructions are not trapped. This is the reset value if Advanced SIMD and Floating-point are
implemented.
1 Instructions are trapped. This is always the value if Advanced SIMD and Floating-point are not
implemented.
[9:0] - Reserved,
RES1.
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
-- -RWRW RW