System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-76
ID021414 Non-Confidential
To access the SCTLR_EL3:
MRS <Xt>, SCTLR_EL3 ; Read SCTLR_EL3 into Xt
MSR SCTLR_EL3, <Xt> ; Write Xt to SCTLR_EL3
4.3.42 Secure Configuration Register
The SCR_EL3 characteristics are:
Purpose Defines the configuration of the security state. SCR_EL3 specifies:
• Security state of EL0 and EL1, either Secure or Non-secure.
• Register width at lower exception levels.
• The exception level that the processor takes exceptions at, if an IRQ,
FIQ, or external abort occurs.
SCR_EL3 is part of the Security registers functional group.
Usage constraints This register is accessible as follows:
Configurations SCR_EL3 is mapped to AArch32 register SCR. See Secure Configuration
Register on page 4-199.
Attributes SCR_EL3 is a 32-bit register.
Figure 4-38 shows the SCR_EL3 bit assignments.
Figure 4-38 SCR_EL3 bit assignments
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
-- --RW RW
To Next Page
Loading...
