ARM Cortex-A53 MPCore - Page 136

System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-75
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Table 4-76 shows the SCTRLR_EL3 bit assignments.
Table 4-76 SCTLR_EL3 bit assignments
Bits Name Function
[31:30] - Reserved,
RES0.
[29:28] - Reserved,
RES1.
[27:26] - Reserved,
RES0.
[25] EE Exception endianness. This bit controls the endianness for:
• Explicit data accesses at EL3.
• Stage 1 translation table walks at EL3.
The possible values are:
0 Little endian. This is the reset value.
1 Big endian.
[24] - Reserved,
RES0.
[23:22] - Reserved,
RES1.
[21:20] - Reserved,
RES0.
[19] WXN Force treatment of all memory regions with write permissions as XN. The possible values are:
0 Regions with write permissions are not forced XN. This is the reset value.
1 Regions with write permissions are forced XN.
[18] - Reserved,
RES1.
[17] - Reserved,
RES0.
[16] - Reserved,
RES1.
[15:13] - Reserved,
RES0.
[12] I Global instruction cache enable. The possible values are:
0 Instruction caches disabled. This is the reset value.
1 Instruction caches enabled.
[11] - Reserved,
RES1.
[10:6] - Reserved,
RES0.
[5:4] - Reserved,
RES1.
[3] SA Enables stack alignment check. The possible values are:
0 Disables stack alignment check.
1 Enables stack alignment check. This is the reset value.
[2] C Global enable for data and unifies caches. The possible values are:
0 Disables data and unified caches. This is the reset value.
1 Enables data and unified caches.
[1] A Enable alignment fault check The possible values are:
0 Disables alignment fault checking. This is the reset value.
1 Enables alignment fault checking.
[0] M Global enable for the EL3 MMU. The possible values are:
0 Disables EL3 MMU. This is the reset value.
1 Enables EL3 MMU.