System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-74
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4.3.40 Hyp Auxiliary Configuration Register
The processor does not implement HACR_EL2, so this register is always
RES0.
4.3.41 System Control Register, EL3
The SCTLR_EL3 characteristics are:
Purpose Provides top level control of the system, including its memory system at
EL3.
SCTLR_EL3 is part of the Virtual memory control registers functional
group.
Usage constraints This register is accessible as follows:
Configurations SCTLR_EL3 is mapped to AArch32 register SCTLR(S). See System
Control Register on page 4-191.
Attributes SCTLR_EL3 is a 32-bit register.
Figure 4-37 shows the SCTLR_EL3 bit assignments.
Figure 4-37 SCTLR_EL3 bit assignments
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
-- --RW RW
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