System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-78
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To access the SCR_EL3:
MRS <Xt>, SCR_EL3 ; Read SCR_EL3 into Xt
MSR SCR_EL3, <Xt> ; Write Xt to SCR_EL3
4.3.43 Secure Debug Enable Register
The SDER32_EL3 characteristics are:
Purpose Allows access to the AArch32 register SDER only from AArch64 state.
Its value has no effect on execution in AArch64 state.
[10] RW Register width control for lower exception levels. The possible values are:
0
Lower levels are all AArch32. This is the reset value.
1
The next lower level is AArch64.
[9] SIF Secure Instruction Fetch. When the processor is in Secure state, this bit disables instruction fetches from
Non-secure memory. The possible values are:
0
Secure state instruction fetches from Non-secure memory are permitted. This is the reset value.
1
Secure state instruction fetches from Non-secure memory are not permitted.
[8] HCE Hyp Call enable. This bit enables the use of
HVC
instructions. The possible values are:
0
The
HVC
instruction is UNDEFINED at all exception levels. This is the reset value.
1
The
HVC
instruction is enabled at EL1, EL2 or EL3.
[7] SMD
SMC
instruction disable. The possible values are:
0
The
SMC
instruction is enabled at EL1, EL2, and EL3. This is the reset value.
1
The
SMC
instruction is UNDEFINED at all exception levels. At EL1, in the Non-secure state, the
HCR_EL2.TSC bit has priority over this control.
[6] - Reserved,
RES0.
[5:4] - Reserved,
RES1.
[3] EA External Abort and SError interrupt Routing. This bit controls which mode takes external aborts. The possible
values are:
0
External Aborts and SError Interrupts while executing at exception levels other than EL3 are not
taken in EL3. This is the reset value.
1
External Aborts and SError Interrupts while executing at all exception levels are taken in EL3.
[2] FIQ Physical FIQ Routing. The possible values ares:
0
Physical FIQ while executing at exception levels other than EL3 are not taken in EL3. This is the
reset value.
1
Physical FIQ while executing at all exception levels are taken in EL3.
[1] IRQ Physical IRQ Routing. The possible values are:
0
Physical IRQ while executing at exception levels other than EL3 are not taken in EL3.
1
Physical IRQ while executing at all exception levels are taken in EL3.
[0] NS Non-secure bit. The possible values are. The possible values are:
0
EL0 and EL1 are in Secure state, memory accesses from those exception levels can access Secure
memory. This is the reset value.
1
EL0 and EL1 are in Non-secure state, memory accesses from those exception levels cannot access
Secure memory.
Table 4-77 SCR_EL3 bit assignments (continued)
Bits Name Function
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