System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-82
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Figure 4-42 CPTR_EL3 bit assignments
Table 4-81 shows the CPTR_EL3 bit assignments.
To access the CPTR_EL3:
MRS <Xt>, CPTR_EL3 ; Read CPTR_EL3 into Xt
MSR CPTR_EL3, <Xt> ; Write Xt to CPTR_EL3
4.3.47 Monitor Debug Configuration Register, EL3
The MDCR_EL3 characteristics are:
Purpose Provides configuration options for Security to self-hosted debug.
Usage constraints This register is accessible as follows:
Configurations MDCR_EL3 is mapped to AArch32 register SDCR. See Secure Debug
Control Register on page 4-204.
Table 4-81 CPTR_EL3 bit assignments
Bits Name Function
[31] TCPAC This causes a direct access to the CPACR_EL1 from EL1 or the CPTR_EL2 from EL2 to trap to EL3 unless it
is trapped at EL2. The possible values are:
0
Does not cause access to the CPACR_EL1 or CPTR_EL2 to be trapped.
1
Causes access to the CPACR_EL1 or CPTR_EL2 to be trapped.
[30:21] - Reserved,
RES0.
[20] TTA Trap Trace Access.
Not implemented.
RES0.
[19:14] - Reserved,
RES0.
[13:12] - Reserved,
RES1.
[11] - Reserved,
RES0.
[10] TFP This causes instructions that access the registers associated with Advanced SIMD or floating-point execution to
trap to EL3 when executed from any exception level, unless trapped to EL1 or EL2. The possible values are:
0
Does not cause any instruction to be trapped.This is the reset value if the Advanced SIMD and
Floating-point Extension is not implemented.
1
Causes any instructions that use the registers associated with Advanced SIMD or floating-point
execution to be trapped. This is always the value if the Advanced SIMD and Floating-point
Extension is not implemented.
[9:0] - Reserved, RES1.
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
-- --RW RW
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