System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-81
ID021414 Non-Confidential
Attributes TTBR1_EL1 is a 64-bit register.
Figure 4-41 shows the TTBR1_EL1 bit assignments.
Figure 4-41 TTBR1_EL1 bit assignments
Table 4-80 shows the TTBR1_EL1 bit assignments.
To access the TTBR1_EL1:
MRS <Xt>, TTBR1_EL1 ; Read TTBR1_EL1 into Xt
MSR TTBR1_EL1, <Xt> ; Write Xt to TTBR1_EL1
4.3.46 Architectural Feature Trap Register, EL3
The CPTR_EL3 characteristics are:
Purpose Controls trapping to EL3 for accesses to CPACR, Trace functionality and
registers associated with Advanced SIMD and Floating-point execution.
Controls EL3 access to this functionality.
CPTR_EL3 is part of the Security registers functional group.
Usage constraints This register is accessible as follows:
Configurations There are no configuration notes.
Attributes CPTR_EL3 is a 32-bit register.
Figure 4-42 on page 4-82 shows the CPTR_EL3 bit assignments.
Table 4-80 TTBR1_EL1 bit assignments
Bits Name Function
[63:48] ASID An ASID for the translation table base address. The TCR_EL1.A1 field selects either TTBR0_EL1.ASID
or TTBR1_EL1.ASID.
[47:0] BADDR[47:x] Translation table base address, bits[47:x]. Bits [x-1:0] are
RES0.
x is based on the value of TCR_EL1.T0SZ, the stage of translation, and the memory translation granule
size.
For instructions on how to calculate it, see the ARM
®
Architecture Reference Manual ARMv8, for
ARMv8-A architecture profile.
The value of x determines the required alignment of the translation table, that must be aligned to 2
x
bytes.
If bits [x-1:0] are not all zero, this is a misaligned Translation Table Base Address. Its effects are
CONSTRAINED UNPREDICTABLE, where bits [x-1:0] are treated as if all the bits are zero. The value read
back from those bits is the value written.
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
-- --RW RW
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