System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-80
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Any of the fields in this register are permitted to be cached in a TLB.
Configurations TTBR0_EL1 is architecturally mapped to AArch32 register TTBR0. See
Translation Table Base Register 0 on page 4-224
Attributes TTBR0_EL1 is 64-bit register.
Figure 4-40 shows the TTBR0_EL1 bit assignments.
Figure 4-40 TTBR0_EL1 bit assignments
Table 4-79 shows the TTBR0_EL1 bit assignments.
To access the TTBR0_EL1:
MRS <Xt>, TTBR0_EL1 ; Read TTBR0_EL1 into Xt
MSR TTBR0_EL1, <Xt> ; Write Xt to TTBR0_EL1
4.3.45 Translation Table Base Register 1
The TTBR1_EL1 characteristics are:
Purpose Holds the base address of translation table 1, and information about the
memory it occupies. This is one of the translation tables for the stage 1
translation of memory accesses at EL0 and EL1.
Usage constraints This register is accessible as follows:
Any of the fields in this register are permitted to be cached in a TLB.
Configurations TTBR1_EL1 is architecturally mapped to AArch32 register TTBR1 (NS).
See Translation Table Base Register 1 on page 4-226.
Table 4-79 TTBR0_EL1 bit assignments
Bits Name Function
[63:48] ASID An ASID for the translation table base address. The TCR_EL1.A1 field selects either TTBR0_EL1.ASID
or TTBR1_EL1.ASID.
[47:0] BADDR[47:x] Translation table base address, bits[47:x]. Bits [x-1:0] are
RES0.
x is based on the value of TCR_EL1.T0SZ, the stage of translation, and the memory translation granule
size.
For instructions on how to calculate it, see the ARM
®
Architecture Reference Manual ARMv8, for
ARMv8-A architecture profile
The value of x determines the required alignment of the translation table, that must be aligned to 2
x
bytes.
If bits [x-1:0] are not all zero, this is a misaligned Translation Table Base Address. Its effects are
CONSTRAINED UNPREDICTABLE, where bits [x-1:0] are treated as if all the bits are zero. The value read
back from those bits is the value written.
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
-RWRWRWRW RW
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