System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-98
ID021414 Non-Confidential
Table 4-89 shows the ESR_EL1 bit assignments.
To access the ESR_EL1:
MRS <Xt>, ESR_EL1 ; Read EL1 Exception Syndrome Register
MSR ESR_EL1, <Xt> ; Write EL1 Exception Syndrome Register
4.3.58 Instruction Fault Status Register, EL2
The IFSR32_EL2 characteristics are:
Purpose Allows access to the AArch32 IFSR register from AArch64 state only. Its
value has no effect on execution in AArch64 state.
Usage constraints This register is accessible as follows:
Configurations IFSR32_EL2 is architecturally mapped to AArch32 register IFSR(NS).
See Instruction Fault Status Register on page 4-243.
Attributes IFSR32_EL2 is a 32-bit register.
There are two formats for this register. The current translation table format determines which
format of the register is used. This section describes:
• IFSR when using the Short-descriptor translation table format on page 4-243.
• IFSR when using the Long-descriptor translation table format on page 4-244.
IFSR32_EL2 when using the Short-descriptor translation table format
Figure 4-51 on page 4-99 shows the IFSR32_EL2 bit assignments when using the
Short-descriptor translation table format.
Table 4-89 ESR_EL1 bit assignments
Bits Name Function
[31:26] EC Exception Class. Indicates the reason for the exception that this register holds information about.
[25] IL Instruction Length for synchronous exceptions. The possible values are:
0
16-bit.
1
32-bit.
This field is 1 for the SError interrupt, instruction aborts, misaligned PC, Stack pointer misalignment, data
aborts for which the ISV bit is 0, exceptions caused by an illegal instruction set state, and exceptions using the
0x00
Exception Class.
[24] ISS Valid Syndrome valid. The possible values are:
0
ISS not valid, ISS is RES0.
1
ISS valid.
[23:0] ISS Syndrome information.
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
-- -RWRW RW
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