System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-97
ID021414 Non-Confidential
4.3.54 Auxiliary Memory Attribute Indirection Register, EL1, EL2 and EL3
The processor does not implement AMAIR_EL1, AMAIR_EL2 and AMAIR_EL3, therefore
these registers are always
RES0.
4.3.55 Auxiliary Fault Status Register 0, EL1, EL2 and EL3
The processor does not implement AFSR0_EL1, AFSR0_EL2 and AFSR0_EL3, therefore
these registers are always
RES0.
4.3.56 Auxiliary Fault Status Register 1, EL1, EL2 and EL3
The processor does not implement AFSR1_EL1, AFSR1_EL2 and AFSR1_EL3, therefore
these registers are always
RES0.
4.3.57 Exception Syndrome Register, EL1
The ESR_EL1 characteristics are:
Purpose Holds syndrome information for an exception taken to EL1.
Usage constraints This register is accessible as follows:
Configurations ESR_EL1 is architecturally mapped to AArch32 register DFSR (NS). See
Data Fault Status Register on page 4-239.
Attributes ESR_EL1 is a 32-bit register.
Figure 4-50 shows the ESR_EL1 bit assignments.
Figure 4-50 ESR_EL1 bit assignments
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
-RWRWRWRW RW
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