System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-96
ID021414 Non-Confidential
To access the TCR_EL3:
MRS <Xt>, TCR_EL3 ; Read EL3 Translation Control Register
MRS TCR_EL3, <Xt> ; Read EL3 Translation Control Register
[22:21] - Reserved, RES0.
[20] TBI Top Byte Ignored. Indicates whether the top byte of the input address is used for address match.
The possible values are:
0
Top byte used in the address calculation.
1
Top byte ignored in the address calculation.
[19] - Reserved,
RES0.
[18:16] PS Physical address size. The possible values are:
0b000
32 bits, 4 GB.
0b001
36 bits, 64 GB.
0b010
40 bits, 1 TB.
Other values are reserved.
[15:14] TG0 TTBR0_EL3 granule size. The possible values are:
0b00
4 KB.
0b10
64 KB.
[13:12] SH0 Shareability attribute for memory associated with translation table walks using TTBR0_EL3.
The possible values are:
0b00
Non-shareable.
0b01
Reserved.
0b10
Outer shareable.
0b11
Inner shareable.
[11:10] ORGN0 Outer cacheability attribute for memory associated with translation table walks using
TTBR0_EL3.
The possible values are:
0b00
Normal memory, Outer Non-cacheable.
0b01
Normal memory, Outer Write-Back Write-Allocate Cacheable.
0b10
Normal memory, Outer Write-Through Cacheable.
0b11
Normal memory, Outer Write-Back no Write-Allocate Cacheable.
[9:8] IRGN0 Inner cacheability attribute for memory associated with translation table walks using
TTBR0_EL3.
The possible values are:
0b00
Normal memory, Inner Non-cacheable.
0b01
Normal memory, Inner Write-Back Write-Allocate Cacheable.
0b10
Normal memory, Inner Write-Through Cacheable.
0b11
Normal memory, Inner Write-Back no Write-Allocate Cacheable.
[7:6] - Reserved,
RES0.
[5:0] T0SZ
Size offset of the memory region addressed by TTBR0_EL3. The region size is 2
(64-T0SZ)
bytes.
Table 4-88 TCR_EL3 bit assignments (continued)
Bits Name Function
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