ARM Cortex-A53 MPCore - Page 161

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Figure 4-52 IFSR32_EL2 bit assignments for Long-descriptor translation table format
Table 4-91 shows the IFSR32_EL2 bit assignments when using the Long-descriptor translation
table format.
Table 4-92 shows how the LL bits in the Status field encode the lookup level associated with the
MMU fault.
31 13 12 11 10 9 8 5 0
RES01
ExT
Status
6
RES0 RES0
Table 4-91 IFSR32_EL2 bit assignments for Long-descriptor translation table format
Bits Name Function
[31:13] - Reserved,
RES0.
[12] ExT External abort type. This field indicates whether an AXI Decode or Slave error caused an abort:
0 External abort marked as DECERR.
1 External abort marked as SLVERR.
For aborts other than external aborts this bit always returns 0.
[11:10] - Reserved,
RES0.
[9] - RAO.
[8:6] - Reserved,
RES0.
[5:0] Status Fault Status bits. This field indicates the type of exception generated. Any encoding not listed is reserved.
0b000000 Address size fault in TTBR0 or TTBR1.
0b0001LL Translation fault, LL bits indicate level.
0b0010LL Access fault flag, LL bits indicate level.
0b0011LL Permission fault, LL bits indicate level.
0b010000 Synchronous external abort.
0b0101LL Synchronous external abort on translation table walk, LL bits indicate level.
0b011000 Synchronous parity error on memory access.
0b0111LL Synchronous parity error on memory access on translation table walk, LL bits indicate level.
0b100001 Alignment fault.
0b100010 Debug event.
0b110000 TLB conflict abort.
Table 4-92 Encodings of LL bits associated with the MMU fault
Bits Meaning
0b00 Reserved
0b01 Level 1
0b10 Level 2
0b11 Level 3