If a Data Abort exception is generated by an instruction cache maintenance operation when the
Long-descriptor translation table format is selected, the fault is reported as a Cache Maintenance
fault in the DFSR or HSR with the appropriate Fault Status code. For such exceptions reported
in the DFSR, the corresponding IFSR32_EL2 is
UNKNOWN.
To access the IFSR32_EL2:
MRS <Xt>, IFSR32_EL2 ; Read IFSR32_EL2 into Xt
MSR IFSR32_EL2, <Xt> ; Write Xt to IFSR32_EL2
Register access is encoded as follows:
4.3.59 Exception Syndrome Register, EL2
The ESR_EL2 characteristics are:
Purpose Holds syndrome information for an exception taken to EL2.
Usage constraints This register is accessible as follows:
Configurations ESR_EL2 is architecturally mapped to AArch32 register HSR. See Hyp
Syndrome Register on page 4-246.
Attributes ESR_EL2 is a 32-bit register.
Figure 4-53 shows the ESR_EL2 bit assignments.
Figure 4-53 ESR_EL2 bit assignments
Table 4-93 IFSR32_EL2 access encoding
op0 op1 CRn CRm op2
11 000 0101 0000 001
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
-- -RWRW RW
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