System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-102
ID021414 Non-Confidential
Table 4-94 shows the ESR_EL2 bit assignments.
To access the ESR_EL2:
MRS <Xt>, ESR_EL2 ; Read EL1 Exception Syndrome Register
MSR ESR_EL2, <Xt> ; Write EL1 Exception Syndrome Register
4.3.60 Exception Syndrome Register, EL3
The ESR_EL3 characteristics are:
Purpose Holds syndrome information for an exception taken to EL3.
Usage constraints This register is accessible as follows:
Configurations ESR_EL3 is mapped to AArch32 register DFSR(S). See Data Fault Status
Register on page 4-239.
Attributes ESR_EL3 is a 32-bit register.
Figure 4-54 shows the ESR_EL3 bit assignments.
Figure 4-54 ESR_EL3 bit assignments
Table 4-94 ESR_EL2 bit assignments
Bits Name Function
[31:26] EC Exception Class. Indicates the reason for the exception that this register holds information about.
[25] IL Instruction Length for synchronous exceptions. The possible values are:
0
16-bit.
1
32-bit.
[24] ISS Valid Syndrome valid. The possible values are:
0
ISS not valid, ISS is RES0.
1
ISS valid.
[23:0] ISS Syndrome information.
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
-- --RW RW
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