System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-103
ID021414 Non-Confidential
Table 4-95 shows the ESR_EL3 bit assignments.
To access the ESR_EL3:
MRS <Xt>, ESR_EL3 ; Read EL3 Exception Syndrome Register
MSR ESR_EL3, <Xt> ; Write EL3 Exception Syndrome Register
4.3.61 Fault Address Register, EL1
The FAR_EL1 characteristics are:
Purpose Holds the faulting Virtual Address for all synchronous instruction or data
aborts, or exceptions from a misaligned PC or a Watchpoint debug event,
taken to EL1.
Usage constraints This register is accessible as follows:
Configurations FAR_EL1[31:0] is architecturally mapped to AArch32 register DFAR
(NS). See Data Fault Address Register on page 4-247.
FAR_EL1[63:32] is architecturally mapped to AArch32 register IFAR
(NS). See Instruction Fault Address Register on page 4-248.
Attributes FAR_EL1 is a 64-bit register.
Figure 4-55 shows the FAR_EL1 bit assignments.
Figure 4-55 FAR_EL1 bit assignments
Table 4-95 ESR_EL3 bit assignments
Bits Name Function
[31:26] EC Exception Class. Indicates the reason for the exception that this register holds information about.
[25] IL Instruction Length for synchronous exceptions. The possible values are:
0
16-bit.
1
32-bit.
This field is 1 for the SError interrupt, instruction aborts, misaligned PC, Stack pointer misalignment, data
aborts for which the ISV bit is 0, exceptions caused by an illegal instruction set state, and exceptions using the
0x0
Exception Class.
[24] ISS Valid Syndrome valid. The possible values are:
0
ISS not valid, ISS is RES0.
1
ISS valid.
[23:0] ISS Syndrome information.
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
-RWRWRWRW RW
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