System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-104
ID021414 Non-Confidential
Table 4-96 shows the FAR_EL1 bit assignments.
To access the FAR_EL1:
MRS <Xt>, FAR_EL1 ; Read EL1 Fault Address Register
MSR FAR_EL1, <Xt> ; Write EL1 Fault Address Register
4.3.62 Fault Address Register, EL2
The FAR_EL2 characteristics are:
Purpose Holds the faulting Virtual Address for all synchronous instruction or data
aborts, or exceptions from a misaligned PC or a Watchpoint debug event,
taken to EL2.
Usage constraints This register is accessible as follows:
Configurations FAR_EL2[31:0] is architecturally mapped to AArch32 registers:
• HDFAR. See Hyp Data Fault Address Register on page 4-249.
• DFAR (S). See Data Fault Address Register on page 4-247.
FAR_EL2[63:32] is architecturally mapped to AArch32 registers:
•HIFAR. See Hyp Instruction Fault Address Register on page 4-250.
• IFAR (S). See Instruction Fault Address Register on page 4-248.
Attributes FAR_EL2 is a 64-bit register.
Figure 4-56 shows the FAR_EL2 bit assignments.
Figure 4-56 FAR_EL2 bit assignments
Table 4-96 FAR_EL1 bit assignments
Bits Name Function
[63:0] VA The faulting Virtual Address for all synchronous instruction or data aborts, or an exception from a misaligned PC,
taken in EL1.
If a memory fault that sets the FAR is generated from one of the data cache instructions, this field holds the address
specified in the register argument of the instruction.
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
-- -RWRW RW
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