System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-110
ID021414 Non-Confidential
If the register must be modified after a powerup reset sequence, to
idle the L2 memory system, you must take the following steps:
1. Disable the MMU from each core followed by an ISB to
ensure the MMU disable operation is complete, then followed
by a DSB to drain previous memory transactions.
2. Ensure that the system has no outstanding AC channel
coherence requests to the Cortex-A53 processor.
3. Ensure that the system has no outstanding ACP requests to the
Cortex-A53 processor.
When the L2 memory system is idle, the processor can update the
L2ACTLR_EL1 followed by an
ISB
. After the L2ACTLR_EL1 is
updated, the MMUs can be enabled and normal ACE and ACP traffic can
resume.
Configurations There is one copy of this register that is used in both Secure and
Non-secure states.
L2ACTLR_EL1 is mapped to the AArch32 L2ACTLR register. See L2
Auxiliary Control Register on page 4-267.
Attributes L2ACTLR_EL1 is a 32 bit register.
Figure 4-60 shows the L2ACTLR_EL1 bit assignments.
Figure 4-60 L2ACTLR_EL1 bit assignments
To Next Page
Loading...
